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TLC393CP

TLC393CP资料
TLC393CP
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Description:An industry-standard design-for-test (DFT) mode is incorporated in the TMS4x100 and TMS4x100P. A CBR cycle with W low (WCBR) cycle is used to enter the test mode. In the test mode, data is written into and read from eight sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data-out terminal goes high. If any one bit is different, the data-out terminal goes low. Any combination of read, write, read-write, or page-mode cycles can be used in the test mode. The test-mode function reduces test times by enabling the 4-Mbit DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10, and column address 0 are not used. A RAS-only or CBR refresh cycle is used to exit the DFT mode.
 
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型 号:TLC393CP
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封 装:
批 号:06+
数 量:1000
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运  费:广东省内10元(平邮),广东省外20元(快递)
所在地:深圳市
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