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| MC74LVXT4066D资料 | |
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MC74LVXT4066D PDF Download |
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File Size : 116 KB
Manufacturer:ON Description:This pin is high if the PLL lock definition is valid. PLL lock definition means the rising edge of REF_IN clock and VCXO_IN clock for PFD are inside the lock detect window for at least five successive input clock cycles. If the rising edge of REF_IN clock and VCXO_IN clock are out of the selected lock detect window, this pin will be low, but it does not refer to the real lock condition of the PLL. See Table 8 and Figure 4. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MC74LVXT4066D 厂 家：ON 封 装：SOP3.9 批 号：04+ 数 量：8492 说 明： |
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运 费：广东省内10元(平邮),广东省外20元(快递) 所在地：深圳市 新旧程度： |
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| 联系人：黄林锋 |
| 电 话：0755-82579969,83255343 |
| 手 机：13714599954, |
| QQ：172517499,137550090 |
| MSN：zfdz168@hotmail.com |
| 传 真：0755-82738881 |
| EMail：zfdz168@163.com |
| 公司地址： 深圳市福田区华强北路华强广场B座28楼L室 |
