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M2764-2F1

M2764-2F1资料
M2764-2F1
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Description:All byte write is done by GW(regardless of BW and WEx.), and each byte write is performed by the combination of BW and WEx when GW is high. Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam- ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa controls DQa0 ~ DQa7, WEb controls DQb0 ~ DQb7, WEc controls DQc0 ~ DQc7, and WEd controls DQd0 ~ DQd7. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
 
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型 号：M2764-2F1
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封 装：
批 号：06+
数 量：1000
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运  费：广东省内10元(平邮),广东省外20元(快递)
所在地：深圳市
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