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| IDT74FST3245SO资料 | |
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IDT74FST3245SO PDF Download |
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File Size : 116 KB
Manufacturer:IDT Description:Target Ready: As a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYN signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a master, this signal indicates that the target is ready for the data during write operation and with the data during read operation. |
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| 相关型号 | |
| ◆ Z9036112PSC | |
| ◆ Z86C6116PSC | |
| ◆ Z84C3006PEC | |
| ◆ Z0861505PSC | |
| ◆ XTR110KP | |
| ◆ XTR106UA | |
| ◆ XTR105UA | |
| ◆ XTR101AP | |
| ◆ XN4601 | |
| ◆ XN4501 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：IDT74FST3245SO 厂 家：IDT 封 装：SOP 批 号：00+ 数 量：5225 说 明： |
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运 费：广东省内10元(平邮),广东省外20元(快递) 所在地：深圳市 新旧程度： |
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