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| HPMX2006资料 | |
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HPMX2006 PDF Download |
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File Size : 116 KB
Manufacturer: Description:The circuits of Figures 1 and 3 depend upon the existence of an output voltage (to create VADJ) and, therefore, produce the initial step-function voltage pedestals of about 1.2V and 1.8V, as can be seen in Figures 2 and 4, respectively. The approach of Figure 5 facilitates placing the output voltage origin at zero volts because VCONTROL is derived from the input voltage. No reactive component is added to the feedback circuit. The value of RT should be considerably smaller than R3 to assure that the junction of RT and CT acts like a voltage source driving R3 and so RT is the primary timing control. If sufficient current is introduced into the loop summing junction (via R3) to generate VADJ VREF, then VOUT will be zero volts. As RT charges CT the voltage VCONTROL decays, which would eventually result in VADJ < VREF. However, since in normal operation VADJ = VREF, VOUT will become greater than zero volts. The process continues until VCONTROL decays to VREF+0.6V and VOUT reaches the desired value. This circuit requires a regulator with an enable function, (e.g., the MIC29152) because a small (< 2V) spike is generated coin- cident with application of a step-function input voltage. Ca- pacitor C1 and resistor R4 provide a short hold-off timing function that eliminates this spike. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：HPMX2006 厂 家： 封 装：SSOP 批 号：98+ 数 量：4534 说 明： |
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运 费：广东省内10元(平邮),广东省外20元(快递) 所在地：深圳市 新旧程度： |
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| 联系人：黄林锋 |
| 电 话：0755-82579969,83255343 |
| 手 机：13714599954, |
| QQ：172517499,137550090 |
| MSN：zfdz168@hotmail.com |
| 传 真：0755-82738881 |
| EMail：zfdz168@163.com |
| 公司地址： 深圳市福田区华强北路华强广场B座28楼L室 |
技术支持:维库电子市场网