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| HEF4066BT资料 | |
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HEF4066BT PDF Download |
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File Size : 116 KB
Manufacturer:PHI Description:INPUT FRAME OFFSET SELECTION Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. F0i). Although input data is synchronous, delays can be caused by variable path serial backplanes and variable path lengths, which may be implemented in large centralized and distributed switching systems. Because data is often delayed this feature is useful in compensating for the skew between clocks. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 7). The frame offset shown is a function of the data rate, and can be as large as +4.5 master clock (CLK) periods forward with a resolution of ½ clock period. To determine the maximum offset allowed see Table 8. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：HEF4066BT 厂 家：PHI 封 装：3.9mm 批 号：99+ 数 量：450 说 明： |
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运 费：广东省内10元(平邮),广东省外20元(快递) 所在地：深圳市 新旧程度： |
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