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| HD74LV86AFPEL资料 | |
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HD74LV86AFPEL PDF Download |
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File Size : 116 KB
Manufacturer:HITACHI Description:The memory, internal to the device, is organized as 32 pages of eight bytes each. Once an address byte is clocked into the device through the 2-wire interface, the five MSBs decode which page is to be accessed, and the three LSBs decode a particular byte on that page. The selected page is shadowed in SRAM as a staging area while data is clocked in or out through the 2-wire interface. When reading any number of bytes, all eight bytes of the current page are shadowed in SRAM where the requested byte(s) eventually get clocked out. When reading, the page is incremented automatically, and hence transparent to the user. When performing a write, the page of the starting address is shadowed in SRAM. The new data is then written to the SRAM. When the end of the page is reached, the address returns to the beginning of the same page. When the 2-wire master issues a stop, the entire page (even if only a single byte changed) is copied from the SRAM into EEPROM. All reads and writes to the EEPROM are actually executed as page operations even though they are invisible to the user when performing single byte reads and writes. Understanding the internal memory organization is important when performing sequential address writes due to page boundaries. See the Write Operations in the 2-WIRE OPERATION section for more information. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：HD74LV86AFPEL 厂 家：HITACHI 封 装：SOP5.2 批 号：00+ 数 量：2000 说 明： |
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运 费：广东省内10元(平邮),广东省外20元(快递) 所在地：深圳市 新旧程度： |
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| 联系人：黄林锋 |
| 电 话：0755-82579969,83255343 |
| 手 机：13714599954, |
| QQ：172517499,137550090 |
| MSN：zfdz168@hotmail.com |
| 传 真：0755-82738881 |
| EMail：zfdz168@163.com |
| 公司地址： 深圳市福田区华强北路华强广场B座28楼L室 |
