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| CD4051BT资料 | |
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CD4051BT PDF Download |
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File Size : 116 KB
Manufacturer:PHI Description:Choose among the following memory organizations: IDT72V2101 262,144 x 9 IDT72V2111 524,288 x 9 Pin-compatible with the IDT72V261/72V271 and the IDT72V281/ 72V291 SuperSync FIFOs 10ns read/write cycle time (6.5ns access time) Fixed, low first word data latency time 5V input tolerant Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Retransmit operation with fixed, low first word data latency time Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets Program partial flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state Easily expandable in depth and width Independent Read and Write clocks (permit reading and writing |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：CD4051BT 厂 家：PHI 封 装：SOP 批 号：05+ 数 量：1000 说 明： |
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运 费：广东省内10元(平邮),广东省外20元(快递) 所在地：深圳市 新旧程度： |
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| 联系人：黄林锋 |
| 电 话：0755-82579969,83255343 |
| 手 机：13714599954, |
| QQ：172517499,137550090 |
| MSN：zfdz168@hotmail.com |
| 传 真：0755-82738881 |
| EMail：zfdz168@163.com |
| 公司地址： 深圳市福田区华强北路华强广场B座28楼L室 |
