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74HC04D

74HC04D资料
74HC04D
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File Size : 116 KB
Manufacturer:PHI
Description:The K7N803645B and K7N801845B are 9,437,184 bits Syn- chronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N803645B and K7N801845B are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP and Multiple power and ground pins minimize ground bounce.
 
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型 号:74HC04D
厂 家:PHI
封 装:SOP
批 号:05+
数 量:5000
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运  费:广东省内10元(平邮),广东省外20元(快递)
所在地:深圳市
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