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| 74ALS04BDR资料 | |
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74ALS04BDR PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2See Figure 2. 3These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 4SCLK active edge is falling edge of SCLK. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin- quish times of the part and as such are independent of external bus loading capacitances. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：74ALS04BDR 厂 家：TI 封 装：3.9mm 批 号：98+ 数 量：2500 说 明： |
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运 费：广东省内10元(平邮),广东省外20元(快递) 所在地：深圳市 新旧程度： |
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| 联系人：黄林锋 |
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