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    技术资料搜索

    DM74S374的技术资料

    来源:深圳市正峰和电子商行    发布时间:2009/4/21 19:55:16   浏览点击数:1759

    DM74S374的产品特征:
    ●Choice of 8 latches or 8 D-type flip-flops in a single package
    3-STATE bus-driving outputs
    Full parallel-access for loading
    Buffered control inputs
    P-N-P input reduce D-C loading on data lines


    DM74S374的技术参数:
    Supply Voltage                                                                       7V
    Input Voltage                                                                      5.5V
    Operating Free Air Temperature Range              0°C to +70°C
    Storage Temperature Range                        −65°C to +150°C
     

    DM74S374的产品描述:

    These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

    The eight latches of the DM74S373 are transparent D-type latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D)inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.

    The eight flip-flops of the DM74S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

    Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

    The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

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